Design Methodology

Low Power Solution

Multi-Vt Cell Swapping

To make customer achieve low power design, Socle delivers Multi-Vt Cell Swapping, PMK(Power Management Kit) insertion, ICG(Isolation Clock Gating)insertion, MSMV(Multi-Supply, Multi-Voltage) design, and Static/Dynamic power analysis.

PMK Cell Insertion

PMK: Power Management Kit

Level Shift Cell: A level shifter cell used by different voltage level(VDDI & VDD)
Isolation Cell: Dedicated isolation cells with one power port. Isolation control will connect to port EN

Retention Cell: State Retention cells with a single retention control port

Switch Cell: Additional cells not in logical netlist. This is the switch defined in the example design library IEEE 1801/UPF/CPF and used in the design P&R netlist

ICG Cell Insertion

ICG(Isolation Clock Gating): Power saving mechanism. When the circuit is idle mode, ICG are used to turn off part of the DFF clock, make the CLK no need to be toggled all the time

ICG cell consists of Latch, And, Not gate

MSMV- Low-Power Equivalence Checking

Define Analysis Style

Set low power option -analysis_style [pre_sim| pre_syn | post_syn | pre_route | post_route]

• PRE_sim(by Customer)
  • RTL design
  • Ready for simulation
  • Check syntax and quality for IEEE 1801/UPF/CPF
• PRE_syn(by Customer)
  • Before gate synthesis
  • Check quality for IEEE 1801/UPF/CPF specification and library
• POST_syn
  • Logical netlist with isolation, level shifter and retention cells
  • Logical netlist without PG connectivity
• PRE_route
  • Before place and route
  • Check quality for IEEE 1801/UPF/CPF specification and library
  • Physical netlist with PG connection
  • Power switch related check
• POST_route
  • Physical netlist with PG connection
  • Check a post place and route netlist with inserted isolation, level shifter, state retention, power switch cells, and power/ground connectivity

Static/Dynamic Power Analysis

Design For Testability

Boundary Scan Design Overview:

Boundary Scan Signal Description:

Scan Design

For scan design, customer need to reply below questions:

• How many clocks by the design?
• Any internally generated clocks?
• Any internally generated asynchronous sets / resets?
• Any tri-state buses?
• How many bi-directional ports by the design?
• Will scan signals be shared with functional signals?
• How to bypass PLL & memories?
• How many scan chains are suitable for the design?
• Any testing time & power issues?

Below is scan chain expample and signal description:

Scan chain count:

Scan Signal Description:

MBIST Design

For MBIST design, customer need to provide number of memories by the design, number of memory controllers by the design, at-function-speed or low speed is necessary, with testing time & power issues or not, and deliver Socle if functional signals shared with MBIST signals.

Below is MBIST design overview and signal description:

MBIST Control Overview:

MBIST Signal Description:

Timing Closure

Timing closure with MMMC(Multi Mode Multi Corner) and on chip variation (OCV) for multiple power domain/on-off domain verification. Socle follow TSMC Recommend Sign Off Corners by difference process node.

Introduction to OCV

OCV : On Chip Variation

Intrinsic variability of semiconductor process, which impact logic timing

SBOCV : Stage Best OCV

SBOCV provide logic depth and/or cell, net location these derate values, to determine how much impacted by the process variation, by specific path design

SOCV : Statistical OCV

SOCV is Gaussian distribution, the nominal delay(µ), and standard deviation(σ) Each cell delay with the highest probability by +/-3σ interval(3 sigma, up to 99.7%)

SOCV variation characterization

- Variation not path based
- Delay = µ + n*σ (µ: Nominal delay; σ: Standard deviation)
- SOCV used LVF file (Liberty Variation Format)
- SOCV consider Gaussian distribution analysis, could be closer ideal derate

OCV type in TSMC process

TSMC Recommend Sign Off Corners

TSMC Recommend Sign Off Corners
- By each mode(Function, DFT) sign off corners